Recently, there has been an active study on a system-on-chip (SOC) in which various devices with different functions have been integrated into one chip. For example, a thick gate dielectric layer is required for devices applied with high voltages to improve reliability, and a thin gate dielectric layer is required for devices sensitive to operation speed. Also, a dual polysilicon gate structure has been studied to improve the device operation speed and to get an N-channel metal oxide semiconductor field effect transistor (NMOSFET) and a P-channel metal oxide semiconductor field effect transistor (PMOSFET) to have a symmetric threshold voltage.
FIG. 1A is a diagram showing a structure of a conventional semiconductor device with a dual gate dielectric layer.
As shown in FIG. 1A, a silicon substrate 11 is divided into a cell region in which NMOS transistors will be formed and a peripheral region in which NMOS transistors and PMOS transistors will be formed. A first gate dielectric layer 12 is formed on the silicon substrate 11 disposed in the cell region, and a second gate dielectric layer 13A is formed on the silicon substrate 11 disposed in a region of the peripheral region where NMOS transistors will be formed. Also, a third gate dielectric layer 13B is formed on the silicon substrate 11 disposed in a region of the peripheral region where PMOS transistors will be formed.
A first gate structure 21 including an n+-type silicon electrode 14A, a low dielectric metal electrode 15 and a gate hard mask 16 is formed on the first gate dielectric layer 12 in the cell region. In the peripheral region, a second gate structure 22 including the n+-type silicon electrode 14A, the low dielectric metal electrode 15 and the gate hard mask 16 is formed on the second insulation layer 13A. Also, a third gate dielectric layer 13B including a p+-type silicon electrode 14B, the low dielectric metal electrode 15 and the gate hard mask 16 is formed on the third gate dielectric layer 13B in the peripheral region.
Herein, the first gate dielectric layer 12 formed in the cell region is thicker than the second and the third gate dielectric layers 13A and 13B formed in the peripheral region. Also, the first and the second gate dielectric layers 12 and 13A are silicon oxide (SiO2) layers formed by employing a thermal oxidation process, while the third gate dielectric layer 13B is a nitride layer.
However, there are several difficulties in forming the first to the third gate dielectric layers with different thicknesses in one chip. First, it is complicated to form the gate dielectric layers 12, 13A and 13B with different thicknesses in different regions through employing a thermal process. Second, the gate dielectric layer 13B formed beneath the P+-type silicon electrode 14B of the PMOS transistor in the peripheral region should be made of nitride instead of oxide in order to prevent penetration of boron. When the gate dielectric layer 13B is made of nitride, nitrogen exists at an interface between the gate dielectric layer 13B and the silicon substrate 11. The nitrogen existing at the interface results in a decrease in mobility of carriers which further causes a device speed to decrease.
FIG. 1B is a graph for comparing normalized transconductance (Gm) of pure silicon oxide with that of nitride.
As shown in FIG. 1B, the nitride has a lower transconductance level than the pure silicon oxide. Generally, it is known that as the transconductance level, which is one parameter for representing a transistor characteristic, is higher, the transistor characteristic becomes better.